The present invention relates to a memory system included in electronic equipment, in particular, a ferroelectric-memory system including a memory cell provided with a ferroelectric capacitor.
Recently, a ferroelectric memory system is proposed in which a capacitance film of a ferroelectric material is disposed in a capacitor of a memory cell so as to make stored data nonvolatile. A ferroelectric material is a material having a characteristic of polarization changed in accordance with a change in the polarity of a voltage (an electric field) in a hysteresis loop as is shown in FIG. 20. Specifically, in a ferroelectric material, as an applied voltage (electric field) is increased, the polarization is increased along a change curve and reaches a saturation polarization value at a point A, and as the voltage (electric field) is decreased, the polarization is gradually decreased not through the above-described change process, and even when the electric field becomes 0, the polarization does not become 0 but residual polarization at a point B remains. When a negative electric field is applied to a ferroelectric material and the electric field is increased in the negative direction, a saturation polarization value is attained at a point C, and when the electric field is decreased to 0, residual polarization at a point D remains. In this manner, a ferroelectric material has a characteristic that residual polarization remains in accordance with the strength and the polarity of an electric field applied theretofore, namely, the so-called hysteresis characteristic. At this point, a saturation polarization value corresponds to a point where the two change curves in the hysteresis curve of FIG. 20 become substantially the same curve, namely, a point where these curves are substantially in contact with each other. Furthermore, the behavior of polarization inversion depends not upon a voltage but upon an electric field given as a value obtained by dividing a voltage by a film thickness, but in the following description, the thickness of a ferroelectric film is fixed, and hence, an operation characteristic in accordance with a voltage will be described.
Therefore, when a ferroelectric capacitor including a ferroelectric film sandwiched between two conductive films is provided in a memory cell and residual polarization of the ferroelectric film in accordance with the polarity and the amplitude of a signal voltage is used as stored data, the stored data can be nonvolatile, and thus, the so-called nonvolatile memory system can be realized.
For example, U.S. Pat. No. 4,873,664 discloses the following two types of ferroelectric memory systems:
In the first type of the nonvolatile memory system, a memory cell includes one transistor and one ferroelectric capacitor (1T1C) per bit. In this case, one dummy memory cell (reference cell) is provided to, for example, every 256 main memory cells (normal cells).
In the second type of the nonvolatile memory system, no dummy memory cell is provided and a memory cell includes two transistors and two ferroelectric capacitors (2T2C) per bit. In this case, a pair of complementary data are stored in a pair of ferroelectric capacitors.
Furthermore, as is disclosed in, for example, U.S. Pat. No. 4,888,733, a memory cell can include two transistors and one ferroelectric capacitor (2T1C) per bit.
Moreover, as a ferroelectric material used in a ferroelectric capacitor, KNO3, PbLa2O3xe2x80x94ZrO2xe2x80x94TiO2, PbTiO3xe2x80x94PbZrO3 and the like are known. Furthermore, PCT International Publication No. WO93/12542 discloses a ferroelectric material suitable to a ferroelectric capacitor used in a ferroelectric memory system that is much less fatigued than PbTiO3xe2x80x94PbZrO3.
On the other hand, ferroelectric materials generally used at present cannot be free from fatigue, and when they are used for a long period of time, their ability to store data can be spoiled.
Therefore, as is disclosed in U.S. Pat. No. 5,532,953, in order not to spoil the ability to store data through usage for a long period of time, a technique to write data at a voltage sufficient for completely saturating a ferroelectric capacitor is used.
Now, the structure and the operation of a ferroelectric memory system disclosed in this publication will be described.
FIG. 21 is an electric circuit diagram for showing the configuration of a memory cell portion of the conventional ferroelectric memory system. In FIG. 21, between a bit line 124 and an inverted bit line 126 and a cell plate line 122 in a memory cell 110, memory cell transistors 112 and 114 and memory cell capacitors 116 and 118 are serially disposed. The gates of the memory cell transistors 112 and 114 are connected with a word line 120. Furthermore, for example, with one of the memory cell capacitors supplied with the residual polarization at the point B (H data) of FIG. 20, and with the other memory cell capacitor supplied with the residual polarization at the point D (L data) of FIG. 20, the polarized state of these two memory capacitors is regarded as data xe2x80x9c1xe2x80x9d. Also, with each of the memory cell capacitors placed in the opposite polarized state to the polarized state of data xe2x80x9c1xe2x80x9d, this opposite polarized state is stored as data xe2x80x9c0xe2x80x9d. By utilizing such complementary data, a ferroelectric memory system with high reliability can be obtained.
Next, read, write (including rewrite) and recovery operations of the conventional ferroelectric memory system will be described. FIGS. 22(a) and 22(b) are flowcharts described in the aforementioned publication as FIGS. 4A and 4B. As is shown in FIG. 22(a), at times t3 and t4, data is read by releasing the charges of the memory cell capacitors 112 and 114 onto the bit line 124 and the inverted bit line 126, and at a time t5, a voltage difference between the bit line 124 and the inverted bit line 126 is sensed through amplification to logical values H and L. Next, at a time t6, a charge pump is operated so as to increase the supply voltage from 4 V to 6 V. Then, by utilizing the increased supply voltage, a write operation is conducted at the time t6. Through the aforementioned procedures, read, sense and write operations are conducted.
Also, as is shown in FIG. 22(b), read, sense and recovery operations are conducted through similar procedures. A recovery operation is an operation for returning the polarized state of a ferroelectric capacitor to a state prior to a read operation.
At this point, the aforementioned publication describes that a write pulse and a release pulse have a width of 20 nanoseconds, and that a read pulse has substantially the same width.
In this manner, in the above-described conventional ferroelectric memory system, a write operation is conducted under application of a voltage necessary for completely saturating a capacitor of a ferroelectric capacitor (the point A of FIG. 20). Specifically, a write operation is conducted at the high voltage (6 V) increased by the charge pump. By adopting such a writing method, the data holding performance of the ferroelectric memory system is to be improved and the life is to be elongated.
However, in the conventional ferroelectric memory system, a write operation is conducted at a higher voltage than a normal voltage so as to completely saturate the ferroelectric capacitor as described above. Accordingly, in order to supply the increased voltage to, for example, a cell plate line PL and a sense amplifier, it is necessary to provide an internal voltage increasing circuit of a charge pump circuit. Since the charge pump circuit is thus provided, there are disadvantages that the entire layout area is increased by the area of circuit elements, such as a capacitor, necessary for the charge pump circuit and that the circuit is complicated. In addition, in accordance with experiment data described below obtained by the present inventors, a write operation conducted so as to completely saturate the polarized state of the ferroelectric capacitor can lead to a disadvantage in a field requiring a high speed operation. Furthermore, an endurance (rewrite) operation, namely, a polarization inverting operation, repeatedly conducted with the polarization completely saturated results in a hysteresis characteristic where the residual polarization decreases. Specifically, it has been found that the ability of holding data can be spoiled.
As the most significant problem, in some usage, a ferroelectric memory system is required to be operated in a wide voltage range of 2 through 6 V, and in such a case, it is difficult to always conduct a write operation at a high voltage sufficient for saturating the polarization.
Moreover, when an operation in a wide voltage range is required, a rewrite operation conducted at a low voltage of approximately 2 V can lead to a read error. In such a case, no examination is made on the mechanism for causing a read error and a method of effectively preventing a read error in any of the ferroelectric memory system of the aforementioned publication and the other conventional ferroelectric memory systems.
A first object of the invention is tracing the cause of a read error and providing means for eliminating the cause, thereby providing a highly reliable ferroelectric memory system and a method of driving the same.
A second object of the invention is providing a ferroelectric memory system capable of a high speed operation without providing an additional circuit such as a charge pump circuit and a method of driving the same.
First, the viewpoint and the fundamental principle of the present invention for achieving the aforementioned objects will be described. As described above, the conventional writing method can lead to a disadvantage in a high speed operation and a phenomenon of a read error which cannot be overcome by the writing method is caused. As a result of tracing the cause of such a read error, it has been found that providing means for overcoming the cause is largely related to solving the problem of the conventional writing method.
First, the present inventors have found that polarization inversion has time dependency so that the polarization inversion can be proceeded with time. Specifically, in the conventional writing method, it has not been noticed that the polarization inverted state of a ferroelectric capacitor depends upon the pulse width (time duration) of a write voltage signal. FIG. 7 is a diagram resulting from examination on variation of the polarization inversion in accordance with the pulse width of a voltage signal in a write and rewrite operation. As is shown in this diagram, the polarization inversion Pnv is largely varied depending upon the width (time duration) of an applied pulse. FIG. 7 will be described in detail below.
Secondly, it has been also found that this time dependency of the polarization inversion Pnv remarkably appears in a region where a voltage applied to a ferroelectric capacitor is low.
Thirdly, it has been also found that the polarization inversion is difficult to proceed at a low temperature. FIG. 8 is a diagram resulting from examination on variation of the polarization inversion Pnv in accordance with the pulse width obtained through a similar experiment to that of FIG. 7 conducted with a pulse voltage fixed to 3 V by using a temperature as a parameter. As is shown in this diagram, it is understood that the polarization inversion is more difficult to proceed at a lower temperature. This implies that, in a ferroelectric capacitor film of polycrystal, domains in the polycrystal include those difficult to polarize and those easy to polarize.
Specifically, the following has been found: Since a ferroelectric capacitor is operated in accordance with such a hysteresis characteristic, there is no need to apply a voltage until the polarized state of a ferroelectric film is completely saturated in writing data in the ferroelectric capacitor, but the memory operation can be easily conducted by adopting an applied voltage or a voltage application time with which a read operation is accurately conducted.
Moreover, as described below, the present inventors have found that the proceeding of the polarization inversion for a write operation can be determined on the basis of an energy to be supplied to a ferroelectric capacitor, namely, a write energy including factors of an applied voltage and a voltage application time, and that the proceeding of the polarization inversion for a read operation can be similarly determined on the basis of a read energy including factors of an applied voltage and a voltage application time.
The present invention achieved through the aforementioned process has the following contents:
The first ferroelectric memory system of this invention comprises a bit line; a cell plate line; a ferroelectric capacitor including a ferroelectric film and disposed between the bit line and the cell plate line; a memory cell transistor disposed between the bit line and the ferroelectric capacitor; writing means for supplying a first energy for polarizing the ferroelectric film to the ferroelectric capacitor through the cell plate line and the bit line; and reading means for supplying a second energy for reading a polarized state of the ferroelectric film to the ferroelectric capacitor through the cell plate line and the bit line, wherein the second energy is smaller than the first energy.
In this manner, a ferroelectric memory system capable of a normal operation without increasing a voltage and a write pulse width (time duration) than necessary can be realized. Specifically, polarization inversion sufficient for a read operation can be conducted without always completely saturating polarization of a ferroelectric capacitor in a write operation. Furthermore, polarization inversion sufficient for a read operation is conducted by elongating a write pulse width (time duration) without increasing a voltage used in a write operation, and thus, a ferroelectric memory system capable of efficient write and read operations can be realized.
In the first ferroelectric memory system, a voltage applied in a write operation can be lower than a saturation voltage for completely saturating polarization of the ferroelectric film, and a voltage value used in a read operation can be made small.
In the ferroelectric memory system thus operated, since there is no need to invert polarization until the complete saturation in a write operation, the write operation can be conducted at a low voltage and a high speed and the polarization is not completely saturated, and therefore, an operation with small power consumption can be attained. Furthermore, since there is no need to provide a charge pump circuit (voltage increasing circuit) for a write operation, the operation with small power consumption can be attained. Moreover, an endurance (rewrite) operation, namely, a polarization inversion operation, repeatedly conducted with the polarization completely saturated results in a hysteresis characteristic in which residual polarization is decreased. Specifically, an ability to hold data can be spoiled. In contrast, when a write operation is conducted without saturating polarization, the ability to hold data can be scarcely spoiled through an endurance (rewrite) operation.
In the first ferroelectric memory system, a read time (pulse width) can be shorter than a write time.
As a result, a ferroelectric memory system with high reading accuracy and high operation speed can be realized.
The second ferroelectric memory system of this invention comprises first and second bit lines; a cell plate line; a first ferroelectric capacitor including a ferroelectric film and disposed between the first bit line and the cell plate line; a second ferroelectric capacitor including a ferroelectric film and disposed between the second bit line and the cell plate line; first and second memory cell transistors respectively disposed between the first and second bit lines and the first and second ferroelectric capacitors; and writing/rewriting control means for conducting a write operation in the ferroelectric film of the first ferroelectric capacitor with a first energy for attaining a first polarized state and subsequently conducting a rewrite operation with a second energy for attaining a second polarized state that is obtained by changing the first polarized state in a direction where a polarity is to be changed, while conducting a write operation in the ferroelectric film of the second ferroelectric capacitor with the first energy for attaining a third polarized state and subsequently conducting a rewrite operation with the second energy for attaining a fourth polarized state that is obtained by changing the third polarized state in a direction where a polarity is to be changed, wherein the first energy and the second energy are supplied in a manner that the first polarized state has an opposite polarity to the second polarized state.
It has been found that a read error can be avoided in this manner even when a read operation is conducted with an energy substantially the same as an energy used in a write operation.
The third ferroelectric memory system of this invention comprises first and second bit lines; a cell plate line; a first ferroelectric capacitor including a ferroelectric film and disposed between the first bit line and the cell plate line; a second ferroelectric capacitor including a ferroelectric film and disposed between the second bit line and the cell plate line; first and second memory cell transistors respectively disposed between the first and second bit lines and the first and second ferroelectric capacitors; writing/rewriting control means for conducting a write operation in the ferroelectric film of the first ferroelectric capacitor with a first energy for attaining a first polarized state and subsequently conducting a rewrite operation with a second energy for attaining a second polarized state that is obtained by changing the first polarized state in a direction where a polarity is to be changed, while conducting a write operation in the ferroelectric film of the second ferroelectric capacitor with the first energy for attaining a third polarized state and subsequently conducting a rewrite operation with the second energy for attaining a fourth polarized state that is obtained by changing the third polarized state in a direction where a polarity is to be changed; and reading control means for conducting a read operation by supplying a third energy to the ferroelectric films of the first and second ferroelectric capacitors through the cell plate line, wherein the third energy is smaller than the second energy.
In this manner, a read error can be prevented in a ferroelectric memory system having a 2T2C memory cell structure.
The fourth ferroelectric memory system of this invention comprises a bit line; a cell plate line; a ferroelectric capacitor including a ferroelectric film and disposed between the bit line and the cell plate line; a memory cell transistor disposed between the bit line and the ferroelectric capacitor; and a writing control circuit for supplying a first energy for polarizing the ferroelectric film of the ferroelectric capacitor between the cell plate line and the bit line, wherein the writing control circuit controls the first energy in a manner that the ferroelectric film is placed in substantially the same polarized state against a temperature change.
In this manner, the polarization inversion of the ferroelectric capacitor can be sufficiently conducted without increasing a write voltage by using a voltage increasing circuit or the like but by sufficiently elongating a write pulse width (time duration), so that a ferroelectric memory system capable of a normal operation at a low voltage can be realized. Furthermore, as a result, a high speed operation can be retained as far as possible even at a low temperature.
The fourth ferroelectric memory system can further comprise reading control means for supplying a second energy for reading a polarized state of the ferroelectric film, and the second energy can be smaller than the first energy.
In the fourth ferroelectric memory system, the writing control circuit can control to conduct a write operation at a higher voltage when a temperature is lower, or the writing control circuit can supply a write signal with a larger pulse width as a temperature is lower.
In the fourth ferroelectric memory system, the writing control circuit can include an internal voltage generation circuit for generating an internal voltage signal that has a lower voltage as a temperature is lower; and a circuit for receiving the internal voltage signal generated by the internal pulse signal generation circuit and generating a pulse signal having a larger pulse width as the voltage of the internal voltage signal is lower.
The first method of this invention of driving a ferroelectric memory system including a ferroelectric capacitor provided with a ferroelectric film and disposed between a bit line and the cell plate line and a memory cell transistor disposed between the bit line and the ferroelectric capacitor, comprises a first step of supplying the ferroelectric capacitor with a first energy for polarizing the ferroelectric film in an unsaturated state; and a second step of supplying the ferroelectric capacitor with a second energy for reading a polarized state of the ferroelectric film, wherein the second energy is smaller than the first energy.
In the first method of driving a ferroelectric memory system, a first pulse signal having a predetermined pulse width can be supplied in the first step, and a second pulse signal having a pulse width smaller than the predetermined pulse width can be supplied in the second step.
The second method of this invention of driving a ferroelectric memory system including first and second ferroelectric capacitors respectively provided with ferroelectric films and disposed between first and second bit lines and a cell plate line, and first and second memory cell transistors respectively disposed between the first and second bit lines and the first and second ferroelectric capacitors, comprises a first step of conducing a write operation in the ferroelectric film of the first ferroelectric capacitor with a first energy for attaining a first polarized state and subsequently conducting a rewrite operation with a second energy for attaining a second polarized state that is obtained by changing the first polarized state in a direction toward an opposite polarity, while conducting a write operation in the ferroelectric film of the second ferroelectric capacitor with the first energy for attaining a third polarized state and subsequently conducting a rewrite operation with the second energy for attaining a fourth polarized state that is obtained by changing the third polarized state in a direction toward an opposite polarity; and a second step of conducting a read operation by supplying a third energy to the ferroelectric films of the first and second ferroelectric capacitors through the cell plate line, wherein the first energy and the second energy are supplied in a manner that the second polarized state has an opposite polarity to the first polarized state.